1. Field of the Invention
The present invention relates to a method for etching an oxide film in a plasma etching system, specifically in a high concentration plasma etching system, in which a mixture of new etching gas chemistry of first, second and third gases is used in forming an oxide film suitable to an integrated circuit with a high device packing density, for improving an etch rate and an etch selectivity of the oxide film to a sub-layer.
2. Discussion of the Related Art
In etching the oxide film, RIE or plasma etching have been used, and recently, high concentration plasma etching has been increasingly used. For an etching gas, though Ar, CF.sub.4, CHF.sub.3 or CHF.sub.3 /O.sub.2 has been used, since they can not provide a satisfactory selectivity to a sub-layer, a gas having a high C/F ratio has been partially applied, recently. As the Ar stabilizes plasma and enhances sputtering, but is not directly involved in any reaction, major etching reaction is caused by CF.sub.4 and CHF.sub.3, and the etch selectivity to a sub-layer in an etching is dependent on a ratio of application of these two gases. That is, when the C/F ratio is high, polymer production is increased to increase the selectivity to the sub-layer, and when the C/F ratio is low, an opposite trend appears. Ar gas flow rate is in a range of 200.about.1000 sccm, and CF.sub.4 and CHF.sub.3 gas flow rates are respectively in a range of 30.about.100 sccm. The flow ratio of these two gases, determined with respect to a desired selectivity, is CF.sub.4 /CHF.sub.3 =0.5.about.1.5. A RF power, dependent on a wafer size and a device structure, is at a level of 700 W to 1300 W. When the remaining photoresist is removed after completion of the etching process, a contact point is formed.
A background art method for fabricating a semiconductor device having the aforementioned oxide film etching applied thereto will be explained. FIGS. 1a.about.1g illustrate sections showing the steps of a background art method for fabricating a semiconductor device having a mixture gas of Ar, CF.sub.4 and CHF.sub.3 /O.sub.2 applied thereto.
Referring to FIG. 1a, a polysilicon film and a silicon nitride film are deposited on a silicon substrate 1 and selectively removed, to form a gate electrode 2 and a cap gate insulating film 3, and the substrate is lightly doped using the gate electrode 2 as a mask, to form lightly doped regions 4 therein. As shown in FIG. 1b, sidewall insulating films 5 of silicon nitride are formed at sides of the gate electrode 2 and the cap gate insulating film 3. As shown in FIG. 1c, the substrate 1 is heavily doped using the sidewall insulating films 5 and the cap gate insulating film 3 as masks, to form source/drain regions 6 therein. As shown in FIG. 1d, an oxide film 7 is deposited on the entire surface. As shown in FIG. 1e, a photoresist film 8 is formed on the oxide film 7 and subjected to exposure and development, to define a bitline contact hole region. The oxide film 7 is selectively removed using the photoresist film 8 as a mask, to form the bitline contact hole. Ar, CF.sub.4 and CHF.sub.3 mixture gas is used in the removal of the oxide film 7. Then, as shown in FIG. 1g, the photoresist film 8 is removed.
In the case of selective removal of the oxide film to form a contact hole as shown in FIG. 1f, if the contact region is not defined accurately due to misalign of mask, a case can be occurred when, not only the nitride films of the sidewall insulating films, but also the polysilicon of the gate electrode are etched in the oxide film etching as shown in FIG. 2, because the oxide film etching with Ar, CF.sub.4 and CHF.sub.3 mixture gas has a low etch selectivity.
Therefore, the background art oxide etching has the following problems.
First, the background art etching has a limitation in securing a selectivity to a sub-layer. That is, though the selectivity is adjusted by using a flow ratio of CF.sub.4 and CHF.sub.3, due to a limitation in an available selectivity, a loss of the sub-layer by the etching can not be controlled to be below 300 .ANG., and the unwanted etching even to the sidewall insulating films and the gate electrode in the contact hole patterning leads to a drop of a yield.
Second, since the microloading effect involved in current gas chemistry of Ar, CF.sub.4, CHF.sub.3 and CHF.sub.3 /O.sub.2 and current etching device does not allow application to an oxide film etching of a small pattern, the background art etching can not be applied to a small sized contact required for an integrated circuit with a high device packing density.
Third, the low etch rate of the background art Ar, CF.sub.4, CHF.sub.3 and CHF.sub.3 /O.sub.2 mixture gas does not allow application to formation of a contact hole with an aspect ratio greater than 3:1.
Fourth, the current chemistry involving high C/F ratio has difficulty in securing an appropriate gas combination and condition, and particularly it has difficulty in regulating the amount of polymer in the plasma, resulting in clogging of the hole or the process not being reproducible. Therefore a level as required in the current device can not be obtained.